CAT25C33_05 Datasheet, PDF (7/11 Pages) Catalyst Semiconductor – 32K/64K-Bit SPI Serial CMOS EEPROM

CAT25C33/65
up in a write disable state when Vcc is applied. WREN and FFFh for 25C33) is reached, the address counter rolls
instruction will enable writes (set the latch) to the device. over to 0000h allowing the read cycle to be continued
WRDI instruction will disable writes (reset the latch) to indefinitely. The read operation is terminated by pulling the
the device. Disabling writes will protect the device CS high. To read the status register, RDSR instruction
against inadvertent writes.
should be sent. The contents of the status register are
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C33/65, followed
by the 16-bit address(the three Most Significant Bits are
shifted out on the SO line. The status register may be read
at any time even during a write cycle. Read sequece is
illustrated in Figure 4. Reading status register is illustrated
in Figure 5.
don’t care for 25C65 and four most significant bits are
don't care for 25C33). After the correct read instruction
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO pin. The
ts ^{data stored in the memory at the next address can be}
read sequentially by continuing to provide clock pulses.
The internal address pointer is automatically incremented
r _{to the next higher address after each byte of data is}
shifted out. When the highest address (1FFFh for 25C65
WRITE Sequence
The CAT25C33/65 powers up in a Write Disable state. Prior
to any write instructions, the WREN instruction must be
sent to CAT25C33/65. The device goes into Write enable
state by pulling the CS low and then clocking the WREN
instruction into CAT25C33/65. The CS must be brought
high after the WREN instruction to enable writes to the
device.
a _{Figure 4. Read Instruction Timing}
P _CS
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
d _SK
e _OPCODE
SI
0000001 1
BYTE ADDRESS*
tinu ^SO
HIGH IMPEDANCE
*Please check the instruction set table for address
DATA OUT
7 6 5 432 1 0
MSB
n _{Note: Dashed Line= mode (1, 1) — — — —}
o _{Figure 5. RDSR Instruction Timing}
c _CS
Dis ^SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
OPCODE
SI
0
0
0
0
0
1
0
1
SO
HIGH IMPEDANCE
DATA OUT
7
6
5
4
3
2
10
MSB
Note: Dashed Line= mode (1, 1) — — — —
© 2005 by Catalyst Semiconductor, Inc.
7
Characteristics subject to change without notice
Doc No. 1000, Rev. H