CAT25C03 Datasheet, PDF (9/10 Pages) Catalyst Semiconductor – 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM

Advanced
CAT25C03/05/09/17/33
DESIGN CONSIDERATIONS
The CAT25C03/05/09/17/33 powers up in a write
disable state and in a low power standby mode. A
WREN instruction must be issued to perform any writes
to the device after power up. Also,on power up CS
should be brought low to enter a ready state and receive
an instruction. After a successful byte/page write or
status register write the CAT25C03/05/09/17/33 goes
into a write disable mode. CS must be set high after the
proper number of clock cycles to start an internal write
cycle. Access to the array during an internal write cycle
Figure 8. Page Write Instruction Timing
is ignored and programming is continued. On power
up, SO is in a high impedance. If an invalid op code is
received, no data will be shifted into the CAT25C03/05/
09/17/33, and the serial output pin (SO) will remain in a
high impedance state until the falling edge of CS is
detected again.
012345678
21 22 23 24-31 32-39
SK
CS
SI
00 00 00 10
SO
Figure 9. HOLD Timing
ADDRESS
Data Data Data
Byte 1 Byte 2 Byte 3
Data
Byte N
CS
SCK
HOLD
SO
tCD
tHD
tHZ
tCD
tHD
tLZ
25C128 F10
9
Doc. No. 25068-00 2/98