CAT25C03 Datasheet, PDF (8/10 Pages) Catalyst Semiconductor – 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM

CAT25C03/05/09/17/33
Advanced
Page Write
The CAT25C03/05/09/17/33 features page write capa-
bility. After the initial byte, the host may continue to write
up to 16 bytes of data to the CAT25C03/05 and 32 bytes
of data for 25C09/17/33. After each byte of data re-
ceived, lower order address bits are internally
incremented by one; the high order bits of address
willremain constant.The only restriction is that the X
(X=16 for 25C03/05 and X=32 for 25C09/17/33) bytes
must reside on the same page. If the address counter
reaches the end of the page and clock continues, the
counter will “roll over” to the first address of the page and
overwrite any data that may have been written. The
CAT25C03/05/09/17/33 is automatically returned to the
write disable state at the completion of the write cycle.
Figure 8 illustrates the page write sequence.
To write to the status register, the WRSR instruction
should be sent. Figure 7 illustrates the sequence of
writing to status register.
Figure 6. Write Instruction Timing
012345678
21 22 23 24 25 26 27 28 29 30 31
SK
CS
SI
00 00 00 10
SO
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
Figure 7. WRSR Timing
CS
SCK
SI
SO
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
INSTRUCTION
DATA IN
7
6
5
4
3
2
1
0
Doc. No. 25068-00 2/98
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