CAT25C03 Datasheet, PDF (3/10 Pages) Catalyst Semiconductor – 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM

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CAT25C03/05/09/17/33
Figure 1. Sychronous Data Timing
V_IH
CS
SCK
SI
V_IL
t_CSS
V_IH
V_IL
V_IH
VIL
t_WH
t_SU
t_H
VALID IN
V_OH
SO
V_OL
HI-Z
A.C. CHARACTERISTICS
t_WL
t_V
t_CS
t_CSH
t_HO
t_DIS
HI-Z
SYMBOL PARAMETER
Limits
1.8, 2.5
4.5V-5.5V
Min.
Max.
Min.
Max.
tSU
Data Setup Time
50
10
tH
Data Hold Time
50
20
tWH
SCK High Time
200
40
tWL
SCK Low Time
200
40
fSCK
tLZ
tRI(1)
tFI(1)
tHD
tCD
Clock Frequency
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD HOLD Time
DC
2
DC
10
50
50
2
2
2
2
100
40
100
40
tWC
Write Cycle Time
10
5
tV
Output Valid from Clock Low
200
80
tHO
Output HOLD Time
0
0
tDIS
Output Disable Time
tHZ
HOLD to Output High Z
tCS
CS High Time
tCSS
CS Setup Time
tCSH
CS HOLD Time
250
75
100
50
250
100
250
100
250
100
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Test
UNITS Conditions
ns VIH = 2.4V
ns CL = 100pF
ns VOL = 0.8V
ns VOH = 2.0v
MHz
ns
µs _{CL = 50pF}
µs
ns
ns CL = 100pF
ms
ns
ns
ns
ns
ns
ns
ns
3
Doc. No. 25068-00 2/98