CAT25C03 Datasheet, PDF (5/10 Pages) Catalyst Semiconductor – 2K/4K/8K/16K/32K SPI Serial CMOS E2PROM

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CAT25C03/05/09/17/33
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication, HOLD is brought high, while SCK is low.
(HOLD should be held high any time this function is not
being used.) HOLD may be tied high directly to VCC or
tied to VCC through a resistor. Figure 9 illustrates hold
timing sequence.
STATUS REGISTER
7
6
5
4
0
0
0
0
MEMORY PROTECTION
IDL2
0
0
0
0
1
1
1
1
IDL1
0
0
1
1
0
0
1
1
IDL0
0
1
0
1
0
1
0
1
Non-Protection
Q1 Protected
Q2 Protected
Q3 Protected
Q4 Protected
H1 Protected
P0 Protected
Pn Protected
STATUS REGISTER
The status register defines the protection status of the
device. The register features three protection bits which
allow the user to protect the desirable part of the memory
array. There are seven different variations for the protec-
tion mechanism. The protection can vary from one page
to as much as half of the entire array. These areas and
associated address ranges are protected by configuring
the protection bits of the status register through WRSR
instruction. Once the three protection bits are set, the
associated memory can be read but not written until the
protection bits are reset.
3
2
1
0
0
IDL2
IDL1
IDL0
25C03 25C05 25C09 25C17 25C33
Q1 00-3F 000-07F 000-0FF 000-1FF 000-3FF
Q2 40-7F 080-0FF 100-1FF 200-3FF 400-7FF
Q3 80-BF 100-17F 200-2FF 400-5FF 800-BFF
Q4 C0-FF 180-1FF 300-3FF 600-7FF C00-FFF
H1 00-7F 000-0FF 000-1FF 000-3FF 000-7FF
P0 00-0F 000-00F 000-01F 000-01F 000-01F
Pn F0-FF 1F0-1FF 3E0-3FF 7E0-7FF FE0-FFF
5
Doc. No. 25068-00 2/98