CAT25640 Datasheet, PDF (9/16 Pages) Catalyst Semiconductor – 64-Kb SPI Serial CMOS EEPROM

CAT25640
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ
instruction followed by a 16-bit address (see Table 5 for
the number of significant address bits).
After receiving the last address bit, the CAT25640 will
respond by shifting out data on the SO pin (as shown
in Figure 8). Sequentially stored data can be read out
by simply continuing to run the clock. The internal
address pointer is automatically incremented to the
next higher address as data is shifted out. After
reaching the highest memory address, the address
counter “rolls over” to the lowest memory address,
and the read cycle can be continued indefinitely. The
read operation is terminated by taking C¯¯S high.
Read Status Register
To read the status register, the host simply sends a
RDSR command. After receiving the last bit of the
command, the CAT25640 will shift out the contents of
the status register on the SO pin (Figure 9). The
status register may be read at any time, including
during an internal write cycle.
Figure 8. READ Timing
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
OPCODE
BYTE ADDRESS*
SI
0 0 0 0 0 0 1 1 ^AN
A0
SO
HIGH IMPEDANCE
* Please check the Byte Address Table (Table 5).
Note: Dashed Line = mode (1, 1) - - - - - -
DATA OUT
7 6 5 432 1 0
MSB
Figure 9. RDSR Timing
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
OPCODE
SI
0
0
0
0
0
SO
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1) - - - - - -
1
0
1
DATA OUT
7
6
5
4
3
2
10
MSB
© Catalyst Semiconductor, Inc.
9
Characteristics subject to change without notice
Doc. No. MD-1128 Rev. B