CAT25640 Datasheet, PDF (8/16 Pages) Catalyst Semiconductor – 64-Kb SPI Serial CMOS EEPROM

CAT25640
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 6. Only
bits 2, 3 and 7 can be written using the WRSR
command.
Write Protection
The Write Protect (¯W¯P¯) pin can be used to protect the
Block Protect bits BP0 and BP1 against being
inadvertently altered. When ¯W¯P¯ is low and the WPEN
bit is set to “1”, write operations to the Status Register
are inhibited. ¯W¯P¯ going low while C¯¯S is still low will
interrupt a write to the status register. If the internal
write cycle has already been initiated, ¯W¯P¯ going low
will have no effect on any write operation to the Status
Register. The ¯W¯P¯ pin function is blocked when the
WPEN bit is set to “0”. The ¯W¯P¯ input timing is shown
in Figure 7.
Figure 6. WRSR Timing
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
OPCODE
SI
0
0
0
0
00
0
SO
HIGH IMPEDANCE
Note: Dashed Line = mode (1, 1) - - - - - -
DATA IN
1
7
6
5
4
32
10
MSB
Figure 7. ¯W¯P¯ Timing
t _WPS
t _WPH
CS
SCK
WP
WP
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1128 Rev. B
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice