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| CAT25640 Datasheet, PDF (2/16 Pages) Catalyst Semiconductor – 64-Kb SPI Serial CMOS EEPROM | |||
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CAT25640
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground(2)
Ratings
â65 to +150
â0.5 to + 6.5
Units
ºC
V
RELIABILITY CHARACTERISTICS(3)
Symbol
NEND(4)
TDR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, TA=-40°C to +85°C unless otherwise specified.
Symbol Parameter
ICCR Supply Current
(Read Mode)
ICCW Supply Current
(Write Mode)
ISB1 Standby Current
ISB2 Standby Current
IL
ILO
VIL
VIH
VOL1
VOH1
VOL2
VOH2
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
Read, VCC = 5.5V, fSCK = 10MHz,
SO open
Write, VCC = 5.5V, fSCK = 10MHz,
SO open
VIN = GND or VCC , C¯¯S = VCC , ¯W¯P¯ = VCC,
VCC = 5.5V
VIN = GND or VCC , C¯¯S = VCC , ¯W¯P¯ = GND,
VCC = 5.5V
VIN = GND or VCC
C¯¯S = VCC , VOUT = GND or VCC
VCC ⥠2.5V, IOL = 3.0mA
VCC ⥠2.5V, IOH = -1.6mA
VCC < 2.5V, IOL = 150µA
VCC < 2.5V, IOH = -100µA
Min
Max Units
2
mA
3
mA
1
µA
3
µA
-2
2
µA
-1
1
µA
-0.5
0.3VCC
V
0.7VCC VCC + 0.5 V
0.4
V
VCC - 0.8V
V
0.2
V
VCC - 0.2V
V
PIN CAPACITANCE(3)
TA = 25ËC, f = 1.0MHz, VCC = +5.0V
Symbol
COUT
CIN
Test
Output Capacitance (SO)
Input Capacitance (C¯¯S, SCK, SI, ¯W¯P¯, H¯¯O¯L¯D¯)
Conditions
VOUT = 0V
VIN = 0V
Min Typ
Max
8
8
Units
pF
pF
Notes:
(1) Stresses above those listed under âAbsolute Maximum Ratingsâ may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5V, 25°C
Doc. No. MD-1128 Rev. B
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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