CAT25640 Datasheet, PDF (6/16 Pages) Catalyst Semiconductor – 64-Kb SPI Serial CMOS EEPROM

CAT25640
WRITE OPERATIONS
The CAT25640 device powers up into a write disable
state. The device contains a Write Enable Latch
(WEL) which must be set before attempting to write to
the memory array or to the status register. In addition,
the address of the memory location(s) to be written
must be outside the protected area, as defined by
BP0 and BP1 bits from the status register.
Write Enable and Write Disable
The internal Write Enable Latch and the correspon–
ding Status Register WEL bit are set by sending the
WREN instruction to the CAT25640. Care must be
taken to take the C¯¯S input high after the WREN
instruction, as otherwise the Write Enable Latch will
not be properly set. WREN timing is illustrated in
Figure 2. The WREN instruction must be sent prior
any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 3. Disabling write
operations by resetting the WEL bit, will protect the
device against inadvertent writes.
Figure 2. WREN Timing
CS
SCK
SI
SO
Note: Dashed Line = mode (1, 1) - - - - - -
0 0 0 00 1 10
HIGH IMPEDANCE
Figure 3. WRDI Timing
CS
SCK
SI
SO
Note: Dashed Line = mode (1, 1) - - - - - -
0 0 0 0 0 1 00
HIGH IMPEDANCE
Doc. No. MD-1128 Rev. B
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice