CAT28F002 Datasheet, PDF (7/16 Pages) Catalyst Semiconductor – 2 Megabit CMOS Boot Block Flash Memory

CAT28F002
ERASE AND PROGRAMMING PERFORMANCE
Parameter
28F002-90
28F002-12
28F002-15
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Boot Block Erase Time
1.0 7
1.0 7
1.0 7 Sec
Parameter Block Erase Time
1.0 7
1.0 7
1.0 7 Sec
Main Block Erase Time
2.4 14
2.4 14
2.4 14 Sec
Main Block Program Time
1.2 4.2
1.2 4.2
1.2 4.2 Sec
FUNCTION TABLE⁽¹⁾
Pins
Mode
Read
RP
CE
OE
WE
VPP
VIH
VIL
VIL
VIH
X
I/O
DOUT
Notes
Output Disable
VIH
VIL
VIH
VIH
X
High-Z
Standby
VIH
VIH
X
X
X
High-Z
Signature (MFG)
VIH
VIL
VIL
VIH
X
31H
A0 = VIL, A9 = 12V
Signature (Device)
V_IH
V_IL
V_IL
V_IH
X 7CH-28F002T A₀ = V_IH, A₉ = 12V
7DH-28F002B
Write Cycle
VIH
VIL
VIH
VIL
X
DIN
During Write Cycle
Deep Power Down
V_IL
X
X
X
X
HIGH-Z
WRITE COMMAND TABLE
Commands are written into the command register in one or two write cycles. The command register can be altered
only when V_PP is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
addresses and data required for programming and erase operations.
Mode
Read Array/Reset
First Bus Cycle
Operation Address D_IN
Write
X
FFH
Second Bus Cycle
Operation Address
D_IN
D_OUT
Program Setup/
Write
AIN
40H
Write
AIN
DIN
Program
10H
Read Status Reg.
Write
X
70H
Read
X
St. Reg. Data
Clear Status Reg.
Write
X
50H
Erase Setup/Erase
Confirm
Write
Block ad 20H
Write Block ad
D0H
Erase Suspend/
Erase Resume
Write
X
B0H
Write
X
D0H
Read Sig (Mfg)
Write
X
90H
Read
0000H
31H
Read Sig (Dev)
Write
X
90H
Note:
(1) Logic Levels: X = Logic ‘Do not care’ (V_IH, V_IL, V_PPL, V_PPH)
Read
0001H
7CH-28F002T
7DH-28F002B
7
Doc. No. 25072-00 2/98 F-1