CAT28F002 Datasheet, PDF (15/16 Pages) Catalyst Semiconductor – 2 Megabit CMOS Boot Block Flash Memory

CAT28F002
ALTERNATE CE-CONTROLLED WRITES
V_CC = +5V ±10%, unless otherwise specified
JEDEC Standard
28F002-90 28F002-12 28F002-15
Symbol Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
tAVAV
tWC Write Cycle Time
90
120
150
ns
tAVEH
tAS Address Setup to CE Going High
50
50
50
ns
tEHAX
tAH Address Hold Time from CE Going High 0
0
0
ns
tDVEH
tDS Data Setup Time to CE Going High
40
40
40
ns
tEHDX
tDH Data Hold Time from CE Going High
0
0
0
ns
tWLEL
tWS WE Setup Time to CE Going Low
0
0
0
ns
tEHWH
tWH WE Hold Time from CE Going High
0
0
0
ns
tELEH
tCP CE Pulse Width
50
50
50
ns
tEHEL
tEPH CE Pulse Width High
30
30
30
ns
tPHEL
tPS(1) RP High Recovery to CE Going Low
215
215
215
ns
tPHHEH
tPHS(1) RP VHH Setup to CE Going High
100
100
100
ns
tVPEH
tVPS(1) VPP Setup to CE Going High
100
100
100
ns
tEHQV1
—
Duration of Programming Operations
6
6
6
µs
tEHQV2
—
Duration of Erase Operations (Boot)
0.3
0.3
0.3
Sec
tEHQV3
—
Duration of Erase Operations (Parameter) 0.3
0.3
0.3
Sec
tEHQV4
—
Duration of Erase Operations (Main)
0.6
0.6
0.6
Sec
tQVVL
tVPH(1) VPP Hold from Valid Status Reg Data
0
0
0
ns
tQVPH
tPHH(1) RP VHH Hold from Status Reg Data
0
0
0
ns
tPHBR(1)
—
Boot Block Relock Delay
100
100
100 ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
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Doc. No. 25072-00 2/98 F-1