CAT28F002 Datasheet, PDF (5/16 Pages) Catalyst Semiconductor – 2 Megabit CMOS Boot Block Flash Memory

CAT28F002
SUPPLY CHARACTERISTICS
Symbol
V_LKO
V_CC
V_PPL
V_PPH
V_HH
V_PPLK
Parameter
V_CC Erase/Write Lock Voltage
V_CC Supply Voltage
V_PP During Read Operations
V_PP During Erase/Program
RP, OE Unlock Voltage
V_PP Lock-Out Voltage
Limits
Min
Max.
Unit
2.0
V
4.5
5.5
V
0
6.5
V
11.4
12.6
V
10.8
13.2
V
0
6.5
V
A.C. CHARACTERISTICS, Read Operation
V_CC = +5V ±10%, unless otherwise specified
JEDEC Standard
Symbol Symbol
Parameter
tAVAV
tRC
Read Cycle Time
tELQV
tCE
CE Access Time
tAVQV
tACC Address Access Time
tGLQV
tOE
OE Access Time
-
tOH
Output Hold from Address OE/CE Change
tGLQX
tOLZ(1)(6) OE to Output in Low-Z
t_ELQX
t_LZ(1)(6) CE to Output in Low-Z
t_GHQZ
t_DF(1)(2) OE High to Output High-Z
t_EHQZ
t_HZ(1)(2) CE High to Output High-Z
t_PHQV
t_PWH RP High to Output Delay
28F002-90 28F002-12 28F002-15
Min. Max. Min. Max. Min. Max. Unit
90
120
150 ns
90
120
150 ns
90
120
150 ns
40
40
40 ns
0
0
0
ns
0
0
0
ns
0
0
0
ns
30
30
30 ns
30
30
30 ns
300
300
300 ns
Figure 1. A.C. Testing Input/Output Waveform^(3)(4)(5)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
5108 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
Note:
CL INCLUDES JIG CAPACITANCE
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V.
(5) Input and Output Timing Reference = 0.8V and 2.0V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
5108 FHD F04
5
Doc. No. 25072-00 2/98 F-1