CAT28F002 Datasheet, PDF (6/16 Pages) Catalyst Semiconductor – 2 Megabit CMOS Boot Block Flash Memory

CAT28F002
A.C. CHARACTERISTICS, Program/Erase Operation
V_CC = +5V ±10%, unless otherwise specified.
JEDEC Standard
28F002-90 28F002-12 28F002-15
Symbol Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
tAVAV
tWC Write Cycle Time
90
120
150
ns
tAVWH
tAS Address Setup to WE Going High
50
50
50
ns
tWHAX
tAH Address Hold Time from WE Going High 0
0
0
ns
tDVWH
tDS Data Setup Time to WE Going High
40
40
40
ns
tWHDX
tDH Data Hold Time from WE Going High
0
0
0
ns
tELWL
tCS CE Setup Time to WE Going Low
0
0
0
ns
tWHEH
tCH CE Hold Time from WE Going High
0
0
0
ns
tWLWH
tWP WE Pulse Width
50
50
50
ns
tWHWL
tWPH WE High Pulse Width
20
20
20
ns
tPHWL
tPS(1) RP to WE Going Low
215
215
215
ns
tPHHWH
tPHS(1) RP VHH Setup to WE Going High
100
100
100
ns
tVPWH
tVPS(1) VPP Setup to WE Going High
100
100
100
ns
tWHQV1
—
Duration of Programming Operations
6
6
6
µs
tWHQV2
—
Duration of Erase Operations (Boot)
0.3
0.3
0.3
Sec
tWHQV3
—
Duration of Erase Operations (Parameter) 0.3
0.3
0.3
Sec
tWHQV4
—
Duration of Erase Operations (Main)
0.6
0.6
0.6
Sec
tQVVL
tVPH(1) VPP Hold from Valid Status Reg Data
0
0
0
ns
tQVPH
tPHH(1) RP VHH Hold from Status Reg Data
0
0
0
ns
tPHBR(1)
—
Boot Block Relock Delay
100
100
100 ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25072-00 2/98 F-1
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