CAT93C76_07 Datasheet, PDF (6/13 Pages) Catalyst Semiconductor – 8K-Bit Microwire Serial EEPROM

CAT93C76 (Rev. A)
Erase
Upon receiving an ERASE command and address,
the CS (Chip Select) pin must be deasserted for a
minimum of t_CSMIN. The falling edge of CS will start the
self clocking clear cycle of the selected memory
location. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C76 can be
determined by selecting the device and polling the DO
pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Erase/Write Enable and Disable
The CAT93C76 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the
EWEN (write enable) instruction. Once the write
instruction is enabled, it will remain enabled until
power to the device is removed, or the EWDS
instruction is sent. The EWDS instruction can be used
to disable all CAT93C76 write and clear instructions,
and will prevent any accidental writing or clearing of
the device. Data can be read normally from the device
regardless of the write enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip
Select) pin must be deselected for a minimum of
t_CSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C76 can be
Figure 4. Erase Instruction Timing
determined by selecting the device and polling the DO
pin. Once cleared, the contents of all memory bits
return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t_CSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C76 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next
rising edge of the clock (SK) in order to start the self-
timed high voltage cycle. This is important because if
CS is brought low before or after this specific frame
window, the addressed location will not be
programmed or erased.
Power-On Reset (POR)
The CAT93C76 incorporates Power-On Reset (POR)
circuitry which protects the device against
malfunctioning while V_CC is lower than the
recommended operating voltage.
The device will power up into a read-only state and
will power-down into a reset state when VCC crosses
the POR level of ~1.3 V.
SK
CS
AN AN-1
A0
DI
11
1
STATUS VERIFY
tCS
STANDBY
tSV
tHZ
HIGH-Z
DO
BUSY READY
HIGH-Z
tEW
Doc. No. MD-1090 Rev. B
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice