CAT93C76_07 Datasheet, PDF (4/13 Pages) Catalyst Semiconductor – 8K-Bit Microwire Serial EEPROM

CAT93C76 (Rev. A)
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V_CC to 0.7V_CC
0.5V_CC
4.5V ≤ V_CC ≤ 5.5V
4.5V ≤ V_CC ≤ 5.5V
1.8V ≤ V_CC ≤ 4.5V
1.8V ≤ V_CC ≤ 4.5V
DEVICE OPERATION
The CAT93C76 is a 8192-bit nonvolatile memory
intended for use with industry standard micropro-
cessors. The CAT93C76 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 13-bit instructions control the read, write and
erase operations of the device. When organized as
X8, seven 14-bit instructions control the read, write
and erase operations of the device. The CAT93C76
operates on a single power supply and will generate
on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The ready/busy status can be determined after the
start of a write operation by selecting the device (CS
high) and polling the DO pin; DO low indicates that the
write operation is not completed, while DO high
indicates that the device is ready for the next
instruction. If necessary, the DO pin may be placed
back into a high impedance state during chip select by
shifting a dummy “1” into the DI pin. The DO pin will
enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high
impedance state is recommended in applications
where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations). The most significant bit of the address
is “don’t care” but it must be present.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C76
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data
bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (t_PD0 or t_PD1).
For the CAT93C76, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will
automatically increment to the next address and shift
out the next data word in a sequential READ mode.
As long as CS is continuously asserted and SK
continues to toggle, the device will keep incrementing
to the next address automatically until it reaches the
end of the address space, then loops back to address
0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All
subsequent data words will follow without a dummy
zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for
a minimum of t_CSMIN. The falling edge of CS will start
the self clocking clear and data store cycle of the
memory location specified in the instruction. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C76 can be
determined by selecting the device and polling the DO
pin. Since this device features Auto-Clear before
write, it is NOT necessary to erase a memory location
before it is written into.
Doc. No. MD-1090 Rev. B
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice