CAT28HT256 Datasheet, PDF (6/10 Pages) Catalyst Semiconductor – 256K-Bit CMOS PARALLEL E2PROM

CAT28HT256
Advanced
Page Write
The page write mode of the CAT28HT256 (essentially
an extended BYTE WRITE mode) allows from 1 to 64
bytes of data to be programmed within a single E²PROM
write cycle. This effectively reduces the byte-write time
by a factor of 64.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 64 byte temporary buffer. The page
address where data is to be written, specified by bits A6
to A14, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A5
Figure 4. Byte Write Cycle [WE Controlled]
ADDRESS
CE
tAS
tAH
tCS
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within tBLC MAX.
Upon completion of the page write sequence, WE must
stay high a minimum of t_{BLC MAX} for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
only write data to the locations that were addressed and
will not rewrite the entire page.
tWC
tCH
OE
WE
DATA OUT
tOES
tWP
HIGH-Z
tOEH
tBLC
DATA IN
DATA VALID
tDS
tDH
Figure 5. Byte Write Cycle [CE Controlled]
tWC
ADDRESS
tAS
CE
tAH
tCW
tBLC
tOEH
OE
tOES
tCS
tCH
WE
DATA OUT
HIGH-Z
DATA IN
DATA VALID
tDS
tDH
5096 FHD F07
Stock No. 21065-03 2/98
8-96
5096 FHD F06