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| CAT28HT256 Datasheet, PDF (2/10 Pages) Catalyst Semiconductor – 256K-Bit CMOS PARALLEL E2PROM | |||
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CAT28HT256
PIN CONFIGURATION
CERDIP Package (D)
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
5096 FHD F01
Advanced
PIN FUNCTIONS
Pin Name
Function
A0âA14
Address Inputs
I/O0âI/O7
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
VCC
5V Supply
VSS
Ground
NC
No Connect
RELIABILITY CHARACTERISTICS
Symbol
NEND(1)
TDR(1)
VZAP(1)
ILTH(1)(2)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
104 or 105
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
MODE SELECTION
Mode
CE
WE
OE
I/O
Power
Read
L
H
L
DOUT
ACTIVE
Byte Write (WE Controlled)
L
H
DIN
ACTIVE
Byte Write (CE Controlled)
L
H
DIN
ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
CI/O(1)
Input/Output Capacitance
CIN(1)
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Latch-up protection is provided for stresses up to 100mA on address and data pins from â1V to VCC +1V.
Stock No. 21065-03 2/98
8-92
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