CAT28HT256 Datasheet, PDF (5/10 Pages) Catalyst Semiconductor – 256K-Bit CMOS PARALLEL E2PROM

Advanced
CAT28HT256
DEVICE OPERATION
Read
Data stored in the CAT28HT256 is transferred to the
data bus when WE is held high, and both OE and CE are
held low. The data bus is set to a high impedance state
when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
Figure 1. A.C. Testing Input/Output Waveform⁽¹⁾
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Note:
(1) Input rise and fall times (10% and 90%) < 10 ns.
5096 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
DEVICE
UNDER
TEST
3.3K
OUT
CL = 100 pF
Figure 3. Read Cycle
ADDRESS
CE
OE
WE
DATA OUT
CL INCLUDES JIG CAPACITANCE
tRC
tCE
tOE
VIH
tLZ
HIGH-Z
tOLZ
tOH
DATA VALID
tAA
5096 FHD F04
tOHZ
tHZ
DATA VALID
8-95
Stock No. 21065-03 2/98