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CAT28HT256 Datasheet, PDF (4/10 Pages) Catalyst Semiconductor – 256K-Bit CMOS PARALLEL E2PROM
CAT28HT256
Advanced
A.C. CHARACTERISTICS, Read Cycle
VCC = 5V ±10%, unless otherwise specified. (Temperature 0˚C to 170˚C)
Symbol
Parameter
tRC
Read Cycle Time
tCE
CE Access Time
tAA
Address Access Time
tOE
OE Access Time
tLZ(1)
CE Low to Active Output
tOLZ(1) OE Low to Active Output
tHZ(1)(4) CE High to High-Z Output
tOHZ(1)(4) OE High to High-Z Output
tOH(1) Output Hold from Address Change
28HT256-20 28HT256-25
Min. Max. Min. Max. Units
200
250
ns
200
250 ns
200
250 ns
80
100 ns
0
0
ns
0
0
ns
50
50 ns
50
50 ns
0
0
ns
A.C. CHARACTERISTICS, Write Cycle
VCC = 5V ±10%, unless otherwise specified. (Temperature 0˚C to 170˚C)
Symbol
Parameter
tWC
Write Cycle Time
tAS
Address Setup Time
tAH
Address Hold Time
tCS
CE Setup Time
tCH
CE Hold Time
tCW(2) CE Pulse Time
tOES
OE Setup Time
tOEH
OE Hold Time
tWP(2) WE Pulse Width
tDS
Data Setup Time
tDH
Data Hold Time
tINIT(1) Write Inhibit Period After Power-up
tBLC(1)(3) Byte Load Cycle Time
28HT256-20 28HT256-25
Min. Max. Min. Max. Units
10
10 ms
0
0
ns
75
75
ns
0
0
ns
0
0
ns
100
100
ns
0
0
ns
0
0
ns
100
100
ns
50
50
ns
10
10
ns
5 10
5 10 ms
0.1 100 0.1 100 µs
Note:
(1) This parameter is tested intitially and after a design or process change that affects the parameter..
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
(4) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Stock No. 21065-03 2/98
8-94