CAT28C17A_04 Datasheet, PDF (6/10 Pages) Catalyst Semiconductor – 16K-Bit CMOS PARALLEL EEPROM

CAT28C17A
DEVICE OPERATION
Read
Data stored in the CAT28C17A is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architec-
ture can be used to eliminate bus contention in a system
environment.
Ready/BUSY (RDY/BUSY)
The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled
low during the write cycle and released at the end of
programming. Several devices may be OR-tied to the
same RDY/BUSY line.
Figure 3. Read Cycle
ADDRESS
CE
OE
WE
DATA OUT
tRC
tCE
tOE
VIH
tLZ
HIGH-Z
tOLZ
tOH
DATA VALID
tAA
tOHZ
tHZ
DATA VALID
Figure 4. Byte Write Cycle [WE Controlled]
ADDRESS
CE
tAS
tAH
tCS
tWC
tCH
OE
WE
RDY/BUSY
DATA OUT
tOES
tWP
tOEH
tDL
tDB
HIGH-Z
DATA IN
Doc. No. 1075, Rev. B
DATA VALID
tDS
tDH
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