CAT28C17A_04 Datasheet, PDF (1/10 Pages) Catalyst Semiconductor – 16K-Bit CMOS PARALLEL EEPROM

CAT28C17A
16K-Bit CMOS PARALLEL EEPROM
FEATURES
■ Fast Read Access Times: 200 ns
■ Low Power CMOS Dissipation:
–Active: 25 mA Max.
–Standby: 100 µA Max.
■ Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
■ Fast Write Cycle Time: 10ms Max
ALOGEN ^FR
LEA _{D F REETM}
■ End of Write Detection:
–DATA Polling
–RDY/BSY Pin
■ Hardware Write Protection
■ CMOS and TTL Compatible I/O
■ 10,000 Program/Erase Cycles
■ 10 Year Data Retention
■ Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28C17A is a fast, low power, 5V-only CMOS
parallel EEPROM organized as 2K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V_CC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and a RDY/BSY pin signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C17A features hardware write protection.
The CAT28C17A is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 10,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 28-pin DIP and SOIC or 32-pin PLCC pack-
ages.
BLOCK DIAGRAM
A4–A10
VCC
CE
OE
WE
A0–A3
RDY/BUSY
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
& RDY/BUSY
COLUMN
DECODER
2,048 x 8
EEPROM
ARRAY
I/O BUFFERS
I/O0–I/O7
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1075, Rev. B