CAT24FC256_05 Datasheet, PDF (6/12 Pages) Catalyst Semiconductor – 256K-Bit I2C Serial CMOS EEPROM

CAT24FC256
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
WRITE OPERATIONS
When all 64 bytes are received, and the STOP condition
Byte Write
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
In the Byte Write mode, the Master device sends the ^{the CAT24FC256 in a single write cycle.}
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
Acknowledge Polling
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24FC256. After receiving
another acknowledge from the Slave, the Master device
t _{transmits the data to be written into the addressed}
r ^{memory location. The CAT24FC256 acknowledges once}
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
a _{cycle to nonvolatile memory. While the cycle is in}
progress, the device will not respond to any request from
P the Master device.
Page Write
The CAT24FC256 writes up to 64 bytes of data, in a
d _{single write cycle, using the Page Write operation. The}
page write operation is initiated in the same manner as
e _{the byte write operation, however instead of terminating}
after the initial byte is transmitted, the Master is allowed
u _{to send up to 63 additional bytes. After each byte has}
been transmitted, CAT24FC256 will respond with an
tin ^{acknowledge, and internally increment the six low order}
address bits by one. The high order bits remain un-
changed.
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24FC256 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24FC256 is still busy with the
write operation, no ACK will be returned. If
CAT24FC256 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to V_CC, the entire memory array is
protected and becomes read only. The CAT24FC256
will accept both slave and byte addresses, but the
memory location accessed is protected from program-
ming by the device’s failure to send an acknowledge
after the first byte of data is received.
Figure 6. Byte Write Timing
n _S
T
o BUS ACTIVITY: A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
S
T
DATA
O
P
c _{SDA LINE S}
P
Dis ^{* *=Don't Care Bit}
A
A
A
A
C
C
C
C
K
K
K
K
Figure 7. Page Write Timing
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
SDA LINE S
*
A
A
A
C
C
C
K
K
K
*^{=Don't Care Bit}
Doc. No. 1040, Rev. K
6
DATA
DATA n
S
T
DATA n+63
O
P
P
A
AA
A
C
CC
C
K
KK
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice