CAT24FC256_05 Datasheet, PDF (3/12 Pages) Catalyst Semiconductor – 256K-Bit I2C Serial CMOS EEPROM

CAT24FC256
AC CHARACTERISTICS
V_CC = 1.8V to 5.5 V, unless otherwise specified. Output load is 1 TTL gate and 100pF.
Read & Write Cycle Limits
Symbol Parameter
VCC=1.8V - 5.5V
VCC=2.5V - 5.5V
Min
Max
Min
Max
Units
F_SCL
Clock Frequency
400
1000
kHz
t_AA
SCL Low to SDA Data Out and
ACK Out
0.05
0.9
0.05
t ⁽²⁾
BUF
Time the Bus Must be Free Before
a New Transmission Can Start
1.3
0.5
t_HD:STA Start Condition Hold Time
0.6
0.25
t_LOW
Clock Low Period
1.3
0.6
t_HIGH
Clock High Period
0.6
0.4
t_SU:STA
Start Condition Setup Time (for a
Repeated Start Condition)
0.6
t_HD:DAT Data In Hold Time
0
d _t
Data In Setup Time
100
SU:DAT
e _t (2)
R
SDA and SCL Rise Time
20
u ^{t (2)}
F
SDA and SCL Fall Time
20
t_SU:STO Stop Condition Setup Time
0.6
tin ^tDH
Data Out Hold Time
50
t_WR
Write Cycle Time
n ^tSP
Input Suppresssion (SDA, SCL)
t_SU;WP
WP Setup Time
0.6
o _tHD;WP
WP Hold Time
1.3
c _{Power-Up Timing (2)(3)}
is ^Symbol
Parameter
t_PUR
Power-Up to Read Operation
D^tPUW
Power-Up to Write Operation
0.25
0
100
0.3
300
0.25
50
5
50
0.5
0.8
Min
Typ
0.5
µs
µs
t_µs
r_µs
Pa ^µs
µs
ns
ns
0.1
µs
100
ns
µs
ns
5
ms
50
ns
µs
µs
Max
Units
1
ms
1
ms
Note:
(1) AC measurement conditions:
RL (connects to V_CC): 0.3V_CC to 0.7 V_CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V_CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1040, Rev. K