CAT24FC256_05 Datasheet, PDF (4/12 Pages) Catalyst Semiconductor – 256K-Bit I2C Serial CMOS EEPROM

CAT24FC256
FUNCTIONAL DESCRIPTION
SDA: Serial Data/Address
The CAT24FC256 supports the I²C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
transfer is controlled by the Master device which WP: Write Protect
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC256 operates ^{This input, when tied to GND, allows write operations to}
as a Slave device. Both the Master device and Slave ^{the entire memory. When this pin is tied to Vcc, the}
device can operate as either transmitter or receiver, but
the Master device controls which mode is activated.
t ^{PIN DESCRIPTIONS}
r _{SCL: Serial Clock}
The serial clock input clocks all data transferred into or
a _{out of the device.}
entire memory is write protected. When left floating,
memory is unprotected.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left connected. When
hardwired, up to eight CAT24FC256's may be addressed
on a single bus system. When the pins are left
unconnected, the default values are zero.
P Figure 1. Bus Timing
tF
d _SCL
e _tSU:STA
u _{SDA IN}
tin ^{SDA OUT}
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
tSU:STO
tBUF
n ^{Figure 2. Write Cycle Timing}
SCL
Disco ^SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1040, Rev. K
4
STOP BIT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice