CAT33C704 Datasheet, PDF (5/14 Pages) Catalyst Semiconductor – 4K-Bit Secure Access Serial E2PROM

Preliminary
CAT33C704
READ SEQUENTIAL
To allow for convenient reading of blocks of contiguous
data, the device has a READ SEQUENTIAL instruction
which accepts a starting address of the block and
continuously outputs data of subsequent addresses
until the end of memory, or until Chip Select goes LOW.
The CAT33C704 communicates with external devices
via a synchronous serial communication protocol (SECS)
that has a maximum transmission rate of 1 MHz. The
data transmission may be a continuous stream of data
or it can be packed by pulsing Chip Select LOW in
between each packet of information. (Except for the
SEQUENTIAL READ instruction where Chip Select
must be held high).
PIN DESCRIPTIONS
CS
Chip Select is a TTL compatible input which, when set
HIGH, allows normal operation of the device. Any time
Chip Select is set LOW, it resets the device, terminating
all I/O communication, and puts the output in a high
impedance state. CS is used to reset the device if an
error condition exists or to put the device in a power-
down mode to minimize power consumption. It may also
be used to frame data transmission in applications
where the clock and data input have to be ignored from
time to time. Although CS resets the device, it does not
change the program/erase or the access-enable status,
nor does it terminate a programming cycle once it has
started. The program/erase and access-enable opera-
tions, once enabled, will remain enabled until specific
disabling instructions are sent or until power is removed.
Figure 3. Unprotected Mode⁽¹⁾
ACCESS REGISTER:
ACCESS CODE LENGTH:
MEMORY POINTER:
x…x
0
a…a
POINTER
REGISTER
ADDRESS
IN MEMORY
READ/WRITE/ERASE
ACCESS
READ-ONLY
ACCESS
255 (x16)
511 (x8)
a…a
0
Figure 4. ERR Pin Timing
CS
CLK
ERR
HIGH-Z
tSV
tSV
Note:
(1) x = DON’T CARE; a = ADDRESS BIT.
5074 FHD F05
5074 FHD F06
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Doc. No. 25046-00 2/98