CAT33C704 Datasheet, PDF (10/14 Pages) Catalyst Semiconductor – 4K-Bit Secure Access Serial E2PROM

CAT33C704
Preliminary
As shipped from the factory, the device is in the unpro-
tected mode. The length of the access code is user
selectable from a minimum of one byte to a maximum of
eight bytes (> 1.84x10¹⁹ combinations). Loading a zero-
length access code will disable protection.
MEMORY POINTER REGISTER
The memory pointer enables the user to segment the
E²PROM array into two sections. In the unprotected
mode, the array can be segmented between read-only
and full access, while in the secure mode, the memory
may be segmented between read-only access and
password-only access. Three instructions are dedicated
to the memory pointer operations. The first one is WMPR
(Write Memory Pointer Register). This instruction, fol-
lowed by an address, will load the memory pointer
register with a new address. This address will be stored
in the E²PROM and can be modified only by another
WMPR instruction. The second instruction is OVMPR
(Override Memory Pointer Register) which allows a
single program/erase to be performed to memory loca-
tions below the address set in the memory pointer. This
instruction allows the user to modify data in a segmented
array without having to move the memory pointer. Once
the operation is complete, the device returns to the
protected mode. If the device is in the secure mode both
of these instructions require the ENAC instruction and a
valid access code prior to their execution. The third
instruction is the RMPR (Read Memory Pointer Regis-
ter) which will place the current contents of the register
in the serial output buffer.
SECS PROTOCOL
The CAT33C704 implements the SECS communication
protocol which uses an 8-bit transmission format. As
shown in Figures 7–13, all instructions are 8 bits long
with the first bit being the start bit and the following 7 bits
being the op-code. Data can be one or two bytes long
depending on the instruction and the memory array
organization. Each address is one or two bytes long
depending on the organization of the memory array. In
this protocol, the transmission of the MSB is always first
and the LSB last. The CS (Chip Select) pin of the
CAT33C704 may be used to frame the data transmis-
sion packet or it may be set HIGH for the entire duration
of operation. If an error in op-code or parity (if enabled)
has been detected, the ERR output will be set LOW and
the CAT33C704 will stop receiving and sending data
until CS is toggled from HIGH to LOW to HIGH again.
Alternatively, an error condition may be detected by
interrogating the device for a status word. If an error
condition has been detected, the DO (Data Output) pin
will not respond. DO may be programmed to become tri-
stated or to output a RDY/BUSY status flag during
program/erase cycles (see ENBSY instruction).
STATUS REGISTER
An eight bit status register is provided to allow the user
to determine the status of the CAT33C704. The contents
of the first three bits of the register are 101 which allows
the user to quickly determine the condition of the device.
The next three bits indicate the status of the device; they
are parity error, instruction error and RDY/BUSY status.
The last two bits are reserved for future use.
CLEAR ALL AND WRITE ALL
As a precaution, the ERAL instruction has to be entered
twice before it is executed. This measure is required as
a redundancy check on the incoming instruction for
possible transmission errors. The WRAL instruction
requires sending an ERAL first (this sets a flag only) and
then the WRAL instruction. The CAT33C704 will accept
Figure 12. WRAL Timing
CS
CLK
DI
OP7
DO
OP CODE
ERAL
OP0 OP7
OP CODE
WRAL
HIGH-Z
OP0
DATA
DON’T CARE
tEW
tSV
READY
BUSY
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