CAT33C704 Datasheet, PDF (11/14 Pages) Catalyst Semiconductor – 4K-Bit Secure Access Serial E2PROM

Preliminary
CAT33C704
the following commands:
ERAL
ERAL
ERAL An ERAL will be executed
WRAL A WRAL will be executed
Both the ERAL and WRAL commands will program/
erase the entire array and will not be blocked by the
memory pointer.
THE PARITY BIT
The SECS protocol supports an even parity bit if the PE
pin of the device is set HIGH, otherwise, there is no
parity. If PE is set LOW and the incoming instruction
contains a parity bit, it may be interpreted as the start bit
of the next instruction. When PE is HIGH, the CAT33C704
expects a parity bit at the end of every incoming instruc-
tion packet. For example, the RSEQ instruction will look
like this:
1100 1011
A15…A8
A7…A0 P
The device then outputs data continuously until it reaches
the end of the memory. The last byte of data contains 9
bits. The ninth bit is the parity bit calculated over the
entire transmitted data packet. The RSEQ instruction
may be terminated at any time by bringing CS low; the
output will then go to high impedance.
SYSTEM ERRORS
Whenever an error occurs, be it an instruction error
(unknown instruction), or parity error (perhaps caused
by transmission error), the device will stop its operation.
To return to normal operation, the device must be reset
by pulsing CS LOW and then set back to HIGH. Reset-
ting the device will not affect the ENAC, EWEN and
ENBSY status. The error may be determined by entering
the READ STATUS REGISTER (RSR) instruction
immediatly following the reset. The status output is an 8
bit word with the first three bits being 101. This three bit
pattern indicates that the device is functioning normally.
The fourth bit is “1” if a parity error occurred. The fifth bit
is a “1” if an instruction error occurred. The sixth bit is a
“1” if the device is in a program/erase cycle. The last two
bits are reserved for future use.
The reason for the “101” pattern is to distinguish be-
tween an error conditon (DO tri-stated) and a device
busy status. If an error condition exists, it will not respond
to any input instruction from DI. However, if the device is
in a program/erase cycle, it responds to the RSR instruc-
tion by outputting “101 00100”. If RSR is executed at the
end of a program/erase cycle, the output will be “101000
00”.
10 1 X X X X X
Figure 13. Next Instruction Timing⁽¹⁾
CS
PARITY
ERROR
INSTRUCTION RDY/BUSY
ERROR
STATUS
FUTURE USE
5074 FHD F09
CLK
tEW
tSV
DI
NEXT INSTRUCTION
HIGH-Z
DO
OP CODE
READY
tHZ
HIGH-Z
BUSY
5074 FHD F16
Note:
(1) DO will be high impedance after the last instruction bit has been clocked in, unless the instruction is RSR or RMPR, in which case, DO will
become active.
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Doc. No. 25046-00 2/98