CAT24WC08W Datasheet, PDF (4/14 Pages) Catalyst Semiconductor – Serial EEPROM

CAT24WC01/02/04/08/16
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The CAT24WC01/02/04/08/16 supports the I²C Bus SCL: Serial Clock
data transmission protocol. This Inter-Integrated Circuit The CAT24WC01/02/04/08/16 serial clock input pin is
Bus protocol defines any device that sends data to the used to clock all data transfers into or out of the device.
bus to be a transmitter and any device receiving data to This is an input pin.
be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
SDA: Serial Data/Address
and STOP conditions for bus access. The CAT24WC01/
The CAT24WC01/02/04/08/16 bidirectional serial data/
02/04/08/16 operates as a Slave device. Both the Mas-
address pin is used to transfer data into and out of the
ter and Slave devices can operate as either transmitter
device. The SDA pin is an open drain output and can be
or receiver, but the Master device controls which mode
is activated. A maximum of 8 devices (CAT24WC01 and
CAT24WC02), 4 devices (CAT24WC04), 2 devices
(CAT24WC08) and 1 device (CAT24WC16) may be
ts ^{connected to the bus as determined by the device}
r ^{address inputs A0, A1, and A2.}
wire-ORed with other open drain or open collector
outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading mul-
tiple devices. When these pins are left floating the
default values are zeros.
A maximum of eight devices can be cascaded when
a _{Figure 1. Bus Timing tF}
P _SCL
d _tSU:STA
e _{SDA IN}
tinu ^{SDA OUT}
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
Figure 2. Write Cycle Timing
tSU:STO
tBUF
5020 FHD F03
n _SCL
Disco ^SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
Doc. No. 1022, Rev. O
START BIT
4
STOP BIT
5020 FHD F05
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice