CAT24WC08W Datasheet, PDF (3/14 Pages) Catalyst Semiconductor – Serial EEPROM

CAT24WC01/02/04/08/16
A.C. CHARACTERISTICS
V_CC = +1.8V to +5.5V, unless otherwise specified.
Read & Write Cycle Limits
CAT24WCXX-1.8
CAT24WCXX
1.8V-5.5V
2.5V-5.5V
4.5V-5.5V
Symbol Parameter
Min. Max. Min. Max. Min. Max. Units
F_SCL
Clock Frequency
100
100
400 kHz
T_I(1)
Noise Suppression Time Constant at
SCL, SDA Inputs
t_AA
SCL Low to SDA Data Out and ACK
Out
ts ^tBUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
r _{tHD:STA Start Condition Hold Time}
4
t_LOW
Clock Low Period
4.7
a _tHIGH
Clock High Period
4
P _tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
t_HD:DAT Data In Hold Time
0
d t_SU:DAT Data In Setup Time
50
t_R(1)
SDA and SCL Rise Time
e _tF(1)
SDA and SCL Fall Time
u ^tSU:STO ^{Stop Condition Setup Time}
4
t_DH
Data Out Hold Time
100
tin ^{Power-Up Timing(1)(2)}
Symbol
Parameter
n _tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
200
200
200 ns
3.5
3.5
1
µs
4.7
1.2
µs
4
0.6
µs
4.7
1.2
µs
4
0.6
µs
4.7
0.6
µs
0
0
ns
50
50
ns
1
1
0.3 µs
300
300
300 ns
4
0.6
µs
100
100
ns
Max.
1
1
Units
ms
ms
co _{Write Cycle Limits}
is ^Symbol
Parameter
D^tWR
Write Cycle Time
Min.
Typ.
Max
10
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1022, Rev. O