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CAT9554A Datasheet, PDF (2/16 Pages) Catalyst Semiconductor – 8-bit I2C and SMBus I/O Port with Interrupt
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CAT9554, CAT9554A
PIN CONFIGURATION
SOIC (W)
TSSOP (Y)
A0 1
A1 2
A2 3
I/O0 4
I/O1 5
I/O2 6
I/O3 7
VSS 8
16 VCC
15 SDA
14 SCL
13 INT
12 I/O7
11 I/O6
10 I/O5
9 I/O4
PIN DESCRIPTION
SOIC / TSSOP
1
2
3
4-7
8
9-12
13
14
15
16
TQFN
15
16
1
2-5
6
7-10
11
12
13
14
TQFN (HV4)
A1 A0 VCC SDA
A2 1
I/O0 2
I/O1 3
I/O2 4
12 SCL
11 INT
10 I/O7
9 I/O6
I/O3 VSS I/O4 I/O5
4 x 4 mm
Top View
PIN NAME
A0
A1
A2
I/O0-3
VSS
I/O4-7
INT
SCL
SDA
VCC
FUNCTION
Address Input 0
Address Input 1
Address Input 2
Input/Output Port 0 to Input/Output Port 3
Ground
Input/Output Port 4 to Input/Output Port 7
Interrupt Output (open drain)
Serial Clock
Serial Data
Power Supply
ABSOLUTE MAXIMUM RATINGS(1)
VCC with Respect to Ground ............... –0.5V to +6.5V
Voltage on Any Pin with
Respect to Ground ........................ –0.5V to +5.5V
DC Current on I/O0 to I/O7 ........................................... +50 mA
DC Input Current ............................................. +20 mA
VCC Supply Current ............................................ 85mA
VSS Supply Current .......................................... 100mA
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Junction Temperature ..................................... +150°C
Storage Temperature ........................ -65°C to +150°C
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Units
VZAP(2)
ESD Susceptibility
JEDEC Standard JESD 22
2000
Volts
ILTH(2)(3)
Latch-up
JEDEC Standard 17
100
mA
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
Doc. No. 25088, Rev. B
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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