CAT9554A Datasheet, PDF (11/16 Pages) Catalyst Semiconductor – 8-bit I2C and SMBus I/O Port with Interrupt

CAT9554, CAT9554A
Power-On Reset Operation
When the power supply is applied to V_CC pin, an internal
power-on reset pulse holds the CAT9554/9554A in a
reset state until V_CC reaches V_POR level. At this point, the
reset condition is released and the internal state ma-
chine and the CAT9554/9554A registers are initialized
to their default state.
slave address
R/W
S 0 1 0 0 A2 A1 A0 0 A
acknowledge from slave
slave address
R/W
COMMAND BYTE
A S 0 1 0 0 A2 A1 A0 1 A
acknowledge from slave
acknowledge from slave
acknowledge
from master
data from register
DATA
A
first byte
At this moment master-transmitter becomes
master-receiver and slave-receiver
becomes slave-transmitter
Figure 11. Read from Register
no acknowledge
from master
data from register
DATA
last byte
NA P
SCL
12 34 56 78 9
slave address
R/W
SDA S 0 1 0 0 A2 A1 A0 1 _A
start condition
acknowledge
from slave
READ FROM
PORT
DATA INTO
PORT
DATA 1
tPH
data from port
DATA 1
A
acknowledge from master
DATA 2
DATA 3
tPS
data from port
DATA 4
NA P
no acknowledge from master
stop
condition
DATA 4
INT
tIV
tIR
Figure 12. Read Input Port Register
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 25088, Rev. B