CAT9555_08 Datasheet, PDF (12/17 Pages) Catalyst Semiconductor – 16-bit I2C and SMBus I/O Port with Interrupt

CAT9555
Power-On Reset Operation
When the power supply is applied to VCC pin, an internal
power-on reset pulse holds the CAT9555 in a reset state
until VCC reaches V_POR level. At this point, the reset
condition is released and the internal state machine and
the CAT9555 registers are initialized to their default
state.
slave address
acknowledge
from slave
acknowledge
from slave
slave address
acknowledge
from slave
data from lower
or upper byte acknowledge
of register
from master
S 0 1 0 0 A2 A1 A0 0 A
R/W
COMMAND BYTE
A S 0 0 1 0 A2 A1 A0 1 A MSB
DATA
LSB A
at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
R/W
first byte
data from upper
or lower byte of
register
no acknowledge
from master
NOTE: Transfer can be stopped at any time by a STOP condition.
Figure 10. Read from Register
MSB
DATA
last byte
LSB NA P
SCL
123456789
I0.x
SDA S 0 1 0 0 A2 A1 A0 1 A
DATA 00
READ FROM PORT 0
R/W ACKNOWLEDGE
FROM SLAVE
t_ph
DATA INTO PORT 0
DATA 00
DATA 01
READ FROM PORT 1
DATA INTO PORT 1
DATA 10
INT
t_IV
t_IR
I1.x
A
DATA 10
ACKNOWLEDGE
FROM MASTER
DATA 02
t_ph
DATA 11
I0.x
A
DATA 03
ACKNOWLEDGE
FROM MASTER
t_ps
DATA 03
I1.x
A
DATA 12
1P
ACKNOWLEDGE
FROM MASTER
NON ACKNOWLEDGE
FROM MASTER
t_ps
DATA 12
NOTE: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to 00 (read input port register).
Figure 11. Read Input Port Register
Doc. No. MD-9003 , Rev. G
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice