CAT9555_08 Datasheet, PDF (10/17 Pages) Catalyst Semiconductor – 16-bit I2C and SMBus I/O Port with Interrupt

CAT9555
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data. The SDA line remains stable LOW during the
HIGH period of the acknowledge related clock pulse
(Figure 7).
The CAT9555 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write operation,
it responds with an acknowledge after receiving each
data byte.
When the CAT9555 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT9555 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT9555 to the standby power
mode and place the device in a known state.
Registers and Bus Transactions
The CAT9555 internal registers and their address and
function are shown in Table 1.
Table 1. Register Command Byte
Command (hex) Register
0h
Input Port 0
1h
Input Port 1
2h
Output Port 0
3h
Output Port 1
4h
Polarity Inversion Port 0
5h
Polarity Inversion Port 1
6h
Configuration Port 0
7h
Configuration Port 1
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine
which register will be written or read.
The input port register is a read only port. It reflects the
incoming logic levels of the I/O pins, regardless of
whether the pin is defined as an input or an output by the
configuration register. Writes to the input port register
are ignored.
Table 2. Registers 0 and 1 – Input Port Registers
bit IO.7 IO.6 IO.5 IO.4 IO.3 IO.2 IO.1 IO.0
default X
X
X
X
X
X
X
X
bit
I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0
default X
X
X
X
X
X
X
X
The default value 'X' is determined by the externally
applied logic lavel
Table 3. Registers 2 and 3 – Output Port Registers
bit O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0
default 1
1
1
1
1
1
1
1
bit O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0
default 1
1
1
1
1
1
1
1
Table 4. Registers 4 and 5 – Polarity Inversion
Registers
bit N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
default 0
0
0
0
0
0
0
0
bit N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
default 0
0
0
0
0
0
0
0
Table 5. Registers 6 and 7 – Configuration Registers
bit C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
default 1
1
1
1
1
1
1
1
bit C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
default 1
1
1
1
1
1
1
1
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
1
8
BUS RELEASE DELAY (RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Doc. No. MD-9003 , Rev. G
ACK DELAY (≤ tAA)
ACK SETUP (≥ tSU:DAT)
Figure 7. Acknowledge Timing
10
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice