CAT24WC03 Datasheet, PDF (7/8 Pages) Catalyst Semiconductor – 2K/4K/8K/16K-Bit Serial E2PROM

Preliminary
CAT24WC03/05/09/17
the low order address bits by one. The high order bits
remain unchanged.
device’s failure to send an acknowledge after the first
byte of data is received.
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be overwrit-
ten.
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24WC03/05/09/17 in a single write cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advan-
tage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24WC03/05/09/17 initiates the inter-
nal write cycle. ACK polling can be initiated immediately.
This involves issuing the start condition followed by the
slave address for a write operation. If the CAT24WC03/
05/09/17 is still busy with the write operation, no ACK will
be returned. If the CAT24WC03/05/09/17 has com-
pleted the write operation, an ACK will be returned and
the host can then proceed with the next read or write
operation.
READ OPERATIONS
The READ operation for the CAT24WC03/05/09/17 is
initiated in the same manner as the write operation with
the one exception that the R/W bit is set to a one. Three
different READ operations are possible: Immediate Ad-
dress READ, Selective READ and Sequential READ.
Immediate Address Read
The CAT24WC03/05/09/17’s address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. If N=E (where E
= 255 for 24WC03, 511 for 24WC05, 1023 for 24WC09,
and 2047 for 24WC17), then the counter will ‘wrap
around’ to address 0 and continue to clock out data.
After the CAT24WC03/05/09/17 receives its slave ad-
dress information (with the R/W bit set to one), it issues
an acknowledge, then transmits the 8-bit byte requested.
The master device does not send an acknowledge but
will generate a STOP condition.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the upper half (locations 80H
to FFH for 24WC03, locations 100H to 1FFH for 24WC05,
locations 200H to 3FFH for 24WC09, locations 400H to
7FFH for 24WC17) of the memory array is protected and
becomes read only. The CAT24WC03/05/09/17 will
accept both slave and byte addresses, but the memory
location accessed is protected from programming by the
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24WC03/05/09/17 acknowledge the
word address, the Master device resends the START
condition and the slave address, this time with the R/W
bit set to one. The CAT24WC03/05/09/17 then responds
with its acknowledge and sends the 8-bit byte requested.
Figure 8. Immediate Address Read Timing
S
T
S
BUS ACTIVITY: ^A
SLAVE
T
MASTER ^R ADDRESS
O
T
P
SDA LINE S
P
A
N
C
DATA
O
K
A
C
K
SCL
8
9
SDA
8TH BIT
DATA OUT
NO ACK
7
STOP
5020 FHD F10
Doc. No. 25063-00 2/98 S-1