CAT24WC03 Datasheet, PDF (5/8 Pages) Catalyst Semiconductor – 2K/4K/8K/16K-Bit Serial E2PROM

Preliminary
CAT24WC03/05/09/17
for 24WC03. If only one 24WC03 is addressed on the
bus, all three address pins (A0, A1, and A2) can be left
floating or connected to VSS
A total of four devices can be addressed on a single bus
when using 24WC05 device. Only A1 and A2 address
pins are used with this device. The A0 address pin is a
no connect pin and can be tied to V_SS or left floating. If
only one 24WC05 is being addressed on the bus, the
address pins (A1 and A2) can be left floating or con-
nected to V_SS.
Only two devices can be cascaded when using 24WC09.
The only address pin used with this device is A2. The A0
and A1address pins are no connect pins and can be tied
to VSS or left floating. If only one 24WC09 is being
addressed on the bus, the address pin (A2) can be left
floating or connected to VSS.
The 24WC17 is a stand alone device. In this case, all
address pins (A0, A1and A2) are no connect pins and
can be tied to VSS or left floating.
WP: Write Protect
If the WP pin is tied to V_CC the upper half of memory array
becomes Write Protected (READ only)(locations 80H to
FFH for 24WC03, locations 100H to 1FFH for 24WC05,
locations 200H to 3FFH for 24WC09, locations 400H to
7FFH for 24WC17). When the WP pin is tied to V_SS or
left floating normal read/write operations are allowed to
the device.
Figure 4. Acknowledge Timing
SCL FROM
1
MASTER
I²C BUS PROTOCOL
The following defines the features of the I²C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC03/05/09/17
monitor the SDA and SCL lines and will not respond until
this condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
24WC03 _{1 0 1 0 A2 A1 A0 R/W}
24WC05 1 0 1 0 A2 A1 a8 R/W
24WC09 1 0 1 0 A2 a9 a8 R/W
24WC17 1 0 1 0 a10 a9 a8 R/W
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8, a9 and a10 correspond to the address of the memory array address word.
***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
5020 FHD F06
5
Doc. No. 25063-00 2/98 S-1