CAT24WC03 Datasheet, PDF (6/8 Pages) Catalyst Semiconductor – 2K/4K/8K/16K-Bit Serial E2PROM

CAT24WC03/05/09/17
Preliminary
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC03/05/09/17 (see Fig. 5). The
next three significant bits (A2, A1, A0) are the device
address bits and define which device or which part of the
device the Master is accessing. Up to eight CAT24WC03,
four CAT24WC05, two CAT24WC09, and one
CAT24WC17 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC03/05/09/17 monitors the
bus and responds with an acknowledge (on the SDA
line) when its address matches the transmitted slave
address. The CAT24WC03/05/09/17 then performs a
Read or Write operation depending on the state of the
R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC03/05/09/17 responds with an acknowl-
edge after receiving a START condition and its slave
address. If the device has been selected along with a
write operation, it responds with an acknowledge after
receiving each 8-bit byte.
When the CAT24WC03/05/09/17 is in a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC03/05/09/17 will con-
tinue to transmit data. If no acknowledge is sent by the
Master, the device terminates data transmission and
waits for a STOP condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24WC03/05/09/17. After receiving
another acknowledge from the Slave, the Master device
transmits the data byte to be written into the addressed
memory location. The CAT24WC03/05/09/17 acknowl-
edge once more and the Master generates the STOP
condition, at which time the device begins its internal
programming cycle to nonvolatile memory. While this
internal cycle is in progress, the device will not respond
to any request from the Master device.
Page Write
The CAT24WC03/05/09/17 writes up to 16 bytes of data
in a single write cycle, using the Page Write operation.
The Page Write operation is initiated in the same manner
as the Byte Write operation, however instead of termi-
nating after the initial word is transmitted, the Master is
allowed to send up to 15 additional bytes. After each byte
has been transmitted the CAT24WC03/05/09/17 will
respond with an acknowledge, and internally increment
Figure 6. Byte Write Timing
S
T
BUS ACTIVITY: ^A
MASTER ^R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
SDA LINE S
P
A
A
A
C
C
C
K
K
K
5020 FHD F08
Figure 7. Page Write Timing
S
T
BUS ACTIVITY: ^A
SLAVE
MASTER ^R ADDRESS
T
SDA LINE S
BYTE
ADDRESS (n)
A
A
C
C
K
K
DATA n
DATA n+1
A
A
C
C
K
K
S
T
DATA n+P ^O
P
P
A
C
K
Doc. No. 25063-00 2/98 S-1
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
6
24WCXX F09
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