CAT24WC03 Datasheet, PDF (4/8 Pages) Catalyst Semiconductor – 2K/4K/8K/16K-Bit Serial E2PROM

CAT24WC03/05/09/17
Preliminary
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The CAT24WC03/05/09/17 supports the I²C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC03/05/
09/17 operates as a Slave device. Both the Master and
Slave devices can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated. A maximum of 8 devices (24WC03), 4 devices
(24WC05), 2 devices (24WC09) and 1 device (24WC17)
may be connected to the bus as determined by the
device address inputs A0, A1, and A2.
SCL: Serial Clock
The CAT24WC03/05/09/17 serial clock input pin is used
to clock all data transfers into or out of the device. This
is an input pin.
SDA: Serial Data/Address
The CAT24WC03/05/09/17 bidirectional serial data/ad-
dress pin is used to transfer data into and out of the
device. The SDA pin is an open drain output and can be
wire-ORed with other open drain or open collector
outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading mul-
tiple devices. When these pins are left floating the
default values are zeros.
Figure 1. Bus Timing _tF
tLOW
tHIGH
A maximum of eight devices can be cascaded when
using 24WC03 device. All three address pins are used
tR
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
5020 FHD F03
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
Doc. No. 25063-00 2/98 S-1
START BIT
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
STOP BIT
4
5020 FHD F05