CAT24FC64 Datasheet, PDF (3/10 Pages) Catalyst Semiconductor – 64K-Bit I2C Serial CMOS EEPROM

CAT24FC64
A.C. CHARACTERISTICS
V_CC = +1.8V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter
VCC=1.8V - 5.5V
VCC=2.5V - 5.5V
Min
Max
Min
Max
Units
F
Clock Frequency
SCL
t_AA
SCL Low to SDA Data Out and
ACK Out
400
1000
kHz
0.05
0.9
0.05
0.5
µs
t ⁽²⁾
BUF
Time the Bus Must be Free Before
a New Transmission Can Start
1.3
0.5
µs
t_HD:STA Start Condition Hold Time
0.6
0.25
µs
t_LOW
Clock Low Period
1.3
0.6
µs
t_HIGH
Clock High Period
0.6
0.4
µs
t_SU:STA
Start Condition Setup Time (for a
Repeated Start Condition)
0.6
0.25
µs
t_HD:DAT
t_SU:DAT
t ⁽²⁾
R
t ⁽²⁾
F
t_SU:STO
t_DH
t_WR
t
SP
t_SU;WP
t_HD;WP
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Input Suppresssion (SDA, SCL)
WP Setup Time
WP Hold Time
0
0
ns
100
100
ns
20
0.3
0.1
µs
20
300
100
ns
0.6
0.25
µs
50
50
ns
5
5
ms
50
50
ns
0.6
0.5
µs
1.3
0.8
µs
Power-Up Timing ⁽²⁾⁽³⁾
Symbol Parameter
Min Typ Max Units
t_PUR Power-Up to Read Operation
100
µs
t_PUW Power-Up to Write Operation
100
µs
Note:
(1) AC measurement conditions:
RL (connects to V_CC): 0.3V_CC to 0.7 V_CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V_CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop interface circuits are disabled, SDA is allowed to remain
condition of a write sequence to the end of the internal high, and the device does not respond to its slave
program/erase cycle. During the write cycle, the bus address.
3
Doc. No. 1046, Rev. G