CM2009 Datasheet, PDF (5/6 Pages) California Micro Devices Corp – VGA Port Companion Circuit

CM2009
Application Information
HSYNC
VSYNC
R1
100k
R2
100k
VCC_5V
VCCA_DAC
RED
GREEN
BLUE
C2
0.2uF
75 75 75
C1
0.2uF
V_{CC_SYNC}
V_{CC_VIDEO}
SYNC_OUT2
SYNC_IN2
SYNC_OUT1
SYNC_IN1
DDC_OUT2
DDC_IN2
DDC_IN1
DDC_OUT1
CM2009
VCCGPIO
** VIDEO Filters.
See Note 4
VIDEO_1
VIDEO_2
VIDEO_3
V_{CC_DDC}
C11
FB4
C12
C9
FB3
C10
C7
FB2
C8
C5
FB1
C6
Optional EMI Filters
VSYNC_OUT
SYNC_GND
HSYNC_OUT
DDC_DATA
DIG_GND
DDC_CLK
RED_VIDEO
GREEN_VIDEO
BLUE_VIDEO
RED_GND
GREEN_GND
BLUE_GND
DDCA_CLK
DDCA_DATA
Video Port
Connector
Figure 1. Typical Application Connection Diagram
NOTES
1 The CM2009 should be placed as close to the VGA or DVI-I connector as possible.
2 The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B signals.
3 If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with external 37.5
resistors.
4 "VF" are external video filters for the RGB signals.
5 Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins. Connections to
the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than 5mm) for best ESD
protection.
6 The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum ESD
withstand voltage at the DDC_OUT pins from ±8kV to ±4kV. If 8kV ESD protection is required, a 0.2µF ceramic bypass
capacitor should be connected between BYP and ground.
7 The SYNC buffers may be used interchangeably between HSYNC and VSYNC.
8 The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference only.
The component values and filter configuration may be changed to suit the application.
9 The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA.
10 R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when no moni-
tor is connected to the VGA connector. If used, it should be noted that "back current" may flow between the DDC pins and
VCC_5V via these resistors when VCC_5V is powered down.
11 For optimal ESD performance with the CM2009-02, an additional clamp device (such as the CMD PACDN042) should be
placed on HSYNC/VSYNC lines between the external matching resistor and the VGA connector.
© 2004 California Micro Devices Corp. All rights reserved.
08/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: [phone] ▲ Fax: [phone] ▲ www.calmicro.com
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