CS4361 Datasheet, PDF (9/23 Pages) Cirrus Logic – 20-pin, 24-bit, 192 kHz, 6-channel D/A Converter

CS4361
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
Parameters
Symbol
Min
Typ
Max
MCLK Frequency
0.512
-
50
MCLK Duty Cycle
45
-
55
Input Sample Rate All MCLK/LRCK ratios combined Fs
2
216
(Note 11)
256x, 384x, 1024x
2
54
256x, 384x
84
134
512x, 768x
42
67
1152x
30
34
128x, 192x
50
108
64x, 96x
100
216
128x, 192x
168
216
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
45
50
55
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Duty Cycle
t_sclkl
20
t_sclkh
20
45
-
-
-
-
50
55
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Internal SCLK Mode
t_slrd
20
-
-
t_slrs
20
-
-
t_sdlrs
20
-
-
t_sdh
20
-
-
LRCK Duty Cycle (Internal SCLK only) (Note 12)
-
50
-
SCLK Period
(Note 13) t_sclkw
----¹---⁰----⁹-----
-
-
SCLK
SCLK rising to LRCK edge
SDIN valid to SCLK rising setup time
t_sclkr
-
t---s---c----l-k----w---
-
2
t_sdlrs
-------1---0----⁹------- + 10
-
-
( 512 ) F s
SCLK rising to SDIN hold time
t_sdh
MCLK / LRCK =1152, 1024, 512, 256, 128, or 64
-------1---0----⁹------- + 15
( 512 ) F s
-
-
SCLK rising to SDIN hold time
t_sdh
MCLK / LRCK = 768, 384, 192, or 96
(^{---3---8-1---40---})^{-9--F----s- + 15}
-
-
Units
MHz
%
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
%
ns
ns
%
ns
ns
ns
ns
%
ns
µs
ns
ns
ns
Notes: 11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on
page 12 for supported ratios and frequencies.
12. In Internal SCLK Mode, the duty cycle must be 50% ± 1/2 MCLK period.
13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on data format and
MCLK/LRCK ratio. (See figures 7-10)
DS672A2
9