CS4361 Datasheet, PDF(12/23 Page) Cirrus Logic – 20-pin, 24-bit, 192 kHz, 6-channel D/A Converter

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CS4361 Datasheet, PDF (12/23 Pages) Cirrus Logic – 20-pin, 24-bit, 192 kHz, 6-channel D/A Converter

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CS4361

4.APPLICATIONS

The CS4361 accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and

64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN). The

Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial Clock

(SCLK) clocks audio data into the input data buffer.

4.1 Master Clock

MCLK/LRCK must be an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the frequency at

which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed mode is de-

tected automatically during the initialization sequence by counting the number of MCLK transitions during a single

LRCK period and by detecting the absolute speed of MCLK. Internal dividers are set to generate the proper clocks.

Table 2 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies. Please note

there is no required phase relationship, but MCLK, LRCK, and SCLK must be synchronous.

LRCK

(kHz)

44.1

88.2

128

176.4

192

Mode

64x

8.1920

11.2896

12.2880

96x

128x

8.1920

11.2896

12.2880

16.9344 22.5792

18.4320 24.5760

QSM

192x

12.2880

16.9344

18.4320

33.8680

36.8640

MCLK (MHz)

256x 384x

8.1920 12.2880

11.2896 16.9344

12.2880 18.4320

22.5792 33.8680

24.5760 36.8640

32.7680 49.1520

DSM

512x

22.5792

24.5760

32.7680

768x 1024x

32.7680

33.8680 45.1580

36.8640 49.1520

49.1520

SSM

1152x

36.8640

Table 2. Common Clock Frequencies

4.2 Serial Clock

The serial clock controls the shifting of data into the input data buffers. The CS4361 supports both external and in-

ternal serial clock generation modes. Refer to Figures 7-10 for data formats.

4.2.1 External Serial Clock Mode

The CS4361 will enter the External Serial Clock Mode when 16 low-to-high transitions are detected on the

DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial Clock

Mode and de-emphasis filter cannot be accessed. The CS4361 will switch to Internal Serial Clock Mode if no

low-to-high transitions are detected on the DEM/SCLK pin for two consecutive frames of LRCK. Refer to

Figure 12.

DS672A2

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