CS4361 Datasheet, PDF (13/23 Pages) Cirrus Logic – 20-pin, 24-bit, 192 kHz, 6-channel D/A Converter

CS4361
4.2.2 Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK.
The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation in this mode
is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the
digital de-emphasis function. Refer to Figures 7 - 12 for details.
LRCK
Left Channel
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
Internal SCLK Mode
External SCLK Mode
I²S, 16-Bit data and INT SCLK = 32 Fs if
I²S, up to 24-Bit Data
MCLK/LRCK = 1024, 512, 256, 128, or 64
I²S, Up to 24-Bit data and INT SCLK = 48 Fs if
Data Valid on Rising Edge of SCLK
MCLK/LRCK = 768, 384, 192, or 96
I²S, Up to 24-Bit data and INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Figure 7. CS4361 Data Format (I²S)
LRCK
Left Channel
Right Channel
SCLK
SDATA
M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B
M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B
Internal SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
External SCLK Mode
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 8. CS4361 Data Format (Left Justified)
DS672A2
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