CS4361 Datasheet, PDF (17/23 Pages) Cirrus Logic – 20-pin, 24-bit, 192 kHz, 6-channel D/A Converter

CS4361
4.6 Output Transient Control
The CS4361 uses Popguard^™ technology to minimize the effects of output transients during power-up and power-
down. When implemented with external DC-blocking capacitors connected in series with the audio outputs, this fea-
ture eliminates the audio transients commonly produced by single-ended, single-supply converters. To make best
use of this feature, it is necessary to understand its operation.
4.6.1 Power-up
When the device is initially powered-up, the audio outputs, AOUT1-6 are clamped to VQ which is initially low.
After RST is released and MCLK is applied, the outputs begin to ramp with VQ towards the nominal quiescent
voltage. This ramp takes approximately 200 ms to complete. The gradual voltage ramping allows time for the
external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Audio output
begins approximately 2000 sample periods after valid LRCK and SDIN are supplied (and SCLK, if used).
4.6.2 Power-down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turning off
the power. In order to do this RST should be held low for a period of about 250 ms before removing power. Dur-
ing this time voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this
250 ms time period has passed a transient will occur when the VA supply drops below that of VQ. There is no
minimum time for a power cycle, power may be re-applied at any time.
When changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present on SDIN
for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always
be in a zero data state. If non-zero audio is present at the time of switching, a slight click or pop may be heard as
the DAC output automatically goes to its zero data state.
4.7 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4361 requires careful attention to power supply and grounding arrange-
ments to optimize performance. Figure 6 shows the recommended power arrangement with VA connected to a clean
+3.3 V or +5 V supply. For best performance, decoupling and filter capacitors should be located as close to the de-
vice package as possible, with the smallest capacitors placed closest.
4.8 Analog Output and Filtering
The analog filter present in the CS4361 is a switched-capacitor filter followed by a continuous-time, low-pass filter.
Its response, combined with that of the digital interpolator, is given in Figures 14 - 21. The recommended external
analog circuitry is shown in the “Typical Connection Diagram” on page 11.
The analog outputs are named AOUT1-6. The SDIN1 feeds AOUT1 as the ‘Left’ marked data and AOUT2 as the
‘Right’ marked data. The SDIN2 feeds AOUT3 as the ‘Left’ marked data and AOUT4 as the ‘Right’ marked data. The
SDIN3 feeds AOUT5 as the ‘Left’ marked data and AOUT6 as the ‘Right’ marked data.
DS672A2
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