CS4228A Datasheet, PDF (9/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228A
SWITCHING CHARACTERISTICS - CONTROL PORT (T_A = 25° C; VA = VD = +5 V,
VL=2.375 to 5.25 V; Inputs: logic 0 = DGND, logic 1 = VL, C_L = 30 pF)
Parameter
Symbol
Min
Max
Units
Two Wire Mode (SDOUT < 47 kΩ to ground)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
f_scl
-
100
kHz
t_buf
4.7
µs
t_hdst
4.0
µs
Clock Low Time
Clock High Time
t_low
4.7
µs
t_high
4.0
µs
Setup Time for Repeated Start Condition
t_sust
4.7
µs
SDA Hold Time from SCL Falling
(Note 12)
t_hdd
0
µs
SDA Setup Time to SCL Rising
t_sud
250
ns
Rise Time of Both SDA and SCL Lines
t_r
1
µs
Fall Time of Both SDA and SCL Lines
t_f
300
ns
Setup Time for Stop Condition
t_susp
4.7
µs
Notes: 12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Stop Start
Repeated
Start
SDA
SCL
t _buf
t _hdst
t _high
t _hdst
t_f
t _low t _hdd
t _sud
t _sust
tr
Figure 4. Two Wire Control Port Timing
Stop
t _susp
DS511PP1
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