CS4228A Datasheet, PDF (21/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228A
5. REGISTER DESCRIPTIONS
All registers are read/write except for Chip Status, which is read only. See the following bit definition tables for bit
assignment information. The default state of each bit after a power-up sequence or reset is listed in the tables un-
derneath each bit’s label. Default values are also marked in the text with an asterisk.
5.1 Memory Address Pointer (MAP)
Not a register
7
INCR
1
6
5
RESERVED
0
0
4
MAP4
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
1
INCR
MAP4:0
memory address pointer auto increment control
0 - MAP is not incremented automatically.
*1 - internal MAP is automatically incremented after each read or write.
Memory address pointer (MAP). Sets the register address that will be read or written by the con-
trol port.
5.2 CODEC Clock Mode
Address 0x01
7
HRM
0
6
5
4
RESERVED
0
0
0
3
2
CI1
CI0
0
1
1
0
RESERVED
0
0
HRM
CI1:0
Sets the sample rate mode for the ADCs and DACs
*0 - Base Rate Mode (BRM) supports sample rates up to 50 kHz
1 - High Rate Mode (HRM) supports sample rates up to 100 kHz. Typically used for
96 kHz sample rate.
Specifies the ratio of MCLK to the sample rate of the ADCs and DACs (Fs)
CI1:0
0
*1
2
3
BRM (Fs)
128
256
384
512
HRM (Fs)
64
128
192
256
DS511PP1
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