CS4228A Datasheet, PDF(26/32 Page) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec　

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

CS4228A Datasheet, PDF (26/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec　

◁

CS4228A

6. PIN DESCRIPTION

Serial Audio Data In 3

Serial Audio Data In 2

Serial Audio Data In 1

Serial Audio Data Out

Serial Clock

Left/Right Clock

Digital Ground

Digital Power

Digital Interface Power

Master Clock

SCL/CCLK

SDA/CDIN

AD0/CS

Reset

SDIN3

SDIN2

SDIN1

SDOUT

SCLK

LRCK

DGND

MCLK

SCL/CCLK

SDA/CDIN

AD0/CS

RST

1 28

2 27

3 26

4 25

5 24

6 23

7 22

8 21

9 20

10 19

11 18

12 17

13 16

14 15

SUB Analog Out #6,Subwoofer

CENTER Analog Out #5, Center

Analog Out #4, Surround Right

Analog Out #3, Surround Left

Analog Out #2, Front Right

Analog Out #1, Front Left

AGND Analog Ground

Analog Power

AINL+ Left Channel Analog Input+

AINL- Left Channel Analog Input-

FILT Internal Voltage Filter

AINR- Right Channel Analog Input-

AINR+ Right Channel Analog Input+

MUTEC Mute Control

SDIN1, SDIN2,

SDIN3

SDOUT

SCLK

1, 2, 3

Serial Audio Data In (Input) - Twoâs complement MSB-first serial audio data is input on this

pin. The data is clocked into SDIN1, SDIN2, SDIN3 via the serial clock and the channel is

determined by the Left/Right clock. The required relationship between the Left/Right clock,

serial clock and serial data is defined by the Serial Mode Register. The options are detailed

in Figures 9, 10, 11, and 12.

Serial Audio Data Out (Output) - Twoâs complement MSB-first serial data is output on this

pin. The data is clocked out of SDOUT via the serial clock and the channel is determined by

the Left/Right clock. The required relationship between the Left/Right clock, serial clock and

serial data is defined by the Serial Mode Register. The options are detailed in Figures 9, 10,

11 and 12.

The state of the SDOUT pin during reset is used to set the Control Port Mode (two wire or

SPI). When RST is low, SDOUT is configured as an input, and the rising edge of RST

latches the state of the pin. A weak internal pull up is present such that a resistive load less

than 47 kâ¦ will pull the pin low, and the control port mode is two wire. When the resistive

load on SDOUT is greater than 47 kâ¦ during reset, the control port mode is SPI.

Serial Clock (Bidirectional) - Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins,

and out of the SDOUT pin. The pin is an output in master mode, and an input in slave

mode.

In master mode, SCLK is configured as an output. MCLK is divided internally to generate

SCLK at the desired multiple of the sample rate.

In slave mode, SCLK is configured as an input. The serial clock can be provided externally,

or the pin can be grounded and the serial clock derived internally from MCLK.

The required relationship between the Left/Right clock, serial clock and serial audio data is

defined by the Serial Port Mode register. The options are detailed in Figures 9, 10, 11, and

12.

DS511PP1

▷