CS4228 Datasheet, PDF (8/30 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228
SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25°C, VD = VL = +3.3V,
VA = +5V; Inputs: logic 0 = DGND, logic 1 = VL+, C_L = 30 pF)
Parameter
Symbol
Min
Max
Units
SPI Mode (SDOUT > 47kΩ to GND)
CCLK Clock Frequency
CS High Time Between Transmissions
f_sck
-
t_csh
1.0
6
MHz
µs
CS Falling to CCLK Edge
t_css
20
ns
CCLK Low Time
t_scl
66
ns
CCLK High Time
t_sch
66
ns
CDIN to CCLK Rising Setup Time
t_dsu
40
ns
CCLK Rising to DATA Hold Time
(Note 9)
t_dh
15
ns
Rise Time of CCLK and CDIN
(Note 10)
t_r2
100
ns
Fall Time of CCLK and CDIN
(Note 10)
t_f2
100
ns
Notes: 9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For F_SCK < 1 MHz
CS
t _css
t _scl t _sch
t _csh
CCLK
t _r2
t _f2
CDIN
t _dsu ^t _dh
Figure 3. SPI Control Port Timing
8
DS307PP1