CS4228 Datasheet, PDF (26/30 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 128x, 256x, 384x or 512x the input sample rate in Base Rate
Mode (BRM) and either 64x, 128x, 192x, or 256x the input sample rate in High Rate Mode (HRM). Table
2 illustrates several standard audio sample rates and the required master clock frequencies. The
MCLK/Fs ration is set by the CI1:0 bits in the CODEC Clock Mode register
Sample
Rate
(kHz)
32
44.1
48
64
88.2
96
64x
-
-
-
4.0960
5.6448
6.1440
HRM
128x
192x
-
-
-
-
-
-
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
MCLK (MHz)
256x
-
-
-
16.3840
22.5792
24.5760
128x
4.0960
5.6448
6.1440
-
-
-
BRM
256x
384x
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
-
-
-
-
-
-
512x
16.3840
22.5792
24.5760
-
-
-
Table 2. Common Master Clock Frequencies
Serial Control Interface Clock - SCL/CCLK
Pin 11, Input
Function:
Clocks serial control data into or out of SDA/CDIN.
Serial Control Data I/O - SDA/CDIN
Pin 12, Bidirectional/Input
Function:
In I²C mode, SDA is a bidirectional control port data line. A pull up resistor must be provided for proper
open drain output operation. In SPI mode, CDIN is the control port data input line. The state of the SDOUT
pin during reset is used to set the control port mode.
Address Bit 0 / Chip Select - ADO/CS
Pin 13, Input
Function:
In I²C mode, AD0 is the LSB of the chip address. In SPI mode, CS is used as a enable for the control port
interface.
Reset - RST
Pin 14, Input
Function:
When low, the device enters a low power mode and all internal registers are reset to the default settings,
including the control port. The control port can not be accessed when reset is low.
When high, the control port and the CODEC become operational.
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DS307PP1