CS4228 Datasheet, PDF (12/30 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228
FUNCTIONAL DESCRIPTION
Overview
The CS4228 is a 24-bit audio codec comprised of 2
analog-to-digital converters (ADC) and 6 digital-
to-analog converters (DAC), all implemented us-
ing single-bit delta-sigma techniques. Other func-
tions integrated with the codec include independent
digital volume controls for each DAC, digital DAC
de-emphasis filters, ADC high-pass filters, an on-
chip voltage reference, and a flexible serial audio
interface. All functions are configured through a
serial control port operable in SPI and I²C compat-
ible modes. Figure 5 shows the recommended con-
nections for the CS4228.
Analog Inputs
Line Level Inputs
AINR+, AINR-, AINL+, and AINL- are the line
level analog inputs (See Figure 5). These pins are
internally biased to a DC operating voltage of ap-
proximately 2.3 VDC. AC coupling the inputs pre-
serves this bias and minimizes signal distortion.
Figure 5 shows operation with a single-ended input
source. This source may be supplied to either the
positive or negative input as long as the unused in-
put is connected to ground through capacitors as
shown. When operated with single-ended inputs,
distortion will increase at input levels higher than
-1 dBFS. Figure 6 shows an example of a differen-
tial input circuit.
Muting of the stereo ADC is possible through the
ADC Control Byte.
The ADC output data is in 2’s complement binary
format. For inputs above positive full scale or be-
low negative full scale, the ADC will output
7FFFFFH or 800000H, respectively.
High Pass Filter
Digital high pass filters in the signal path after the
ADCs remove any DC offsets present on the analog
4.7 k
10 µF
10 k
signal
-
+
+
10 k
10 k
10 k
VA
~ 8.5 k
+
10 µf
+
-
0.1µF
150
AIN -
2.2 nf
150
AIN +
Figure 6. Optional Line Input Buffer
inputs. This helps to prevent audible "clicks" when
switching the audio in devices downstream from
the ADCs. The high pass filter response, given in
“High Pass Filter Characteristics” on page 4, scales
linearly with sample rate. Thus, for High Rate
Mode, the -3 dB frequency at a 96 kHz sample rate
will be equal to 96/44.1 times that at a sample rate
of 44.1 kHz.
The high pass filters can be disabled by setting the
HPF bit in the ADC Control register. When assert-
ed, any DC present at the analog inputs will be rep-
resented in the ADC outputs. The high pass filter
may also be “frozen” using the HPFZ bit in the
ADC Control register. In this condition, it will re-
member the DC offset present at the ADC inputs at
the moment the HPFZ bit was asserted, and will
continue to remove this DC level from the ADC
outputs. This is useful in cases where it is desirable
to eliminate a fixed DC offset while still maintain-
ing full frequency response down to DC.
Analog Outputs
Line Level Outputs
The CS4228 contains on-chip buffer amplifiers ca-
pable of producing line level outputs. These ampli-
fiers are biased to a quiescent DC level of
approximately 2.3 V. This bias, as well as varia-
tions in offset voltage, are removed using off-chip
AC load coupling.
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DS307PP1