EP9315 Datasheet, PDF (61/64 Pages) Cirrus Logic – Enhanced Universal Platform System-on-Chip Processor

EP9315
Enhanced Universal Platform SOC Processor
Table S. Pin Descriptions (Continued)
Pin Name
Block
Pad Pull
Type Type
Description
MDIO
RXCLK
MIIRXD[3:0]
RXDVAL
RXERR
TXCLK
MIITXD[3:0]
TXEN
TXERR
CRS
CLD
GRLED
RDLED
EECLK
EEDAT
ABITCLK
ASYNC
ASDI
ASDO
ARSTn
SCLK1
SFRM1
SSPRX1
SSPTX1
INT[3:0]
PRSTn
RSTOn
SLA[1:0]
VS1
VS2
MCD1
MCD2
MCBVD1
MCBVD2
MCDIR
MCDAENn
MCADENn
MCREGn
MCEHn
MCELn
IORDn
IOWRn
MCRDn
MCWRn
READY
WP
MCWAITn
MCRESETn
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
LED
LED
EEPROM
EEPROM
AC97
AC97
AC97
AC97
AC97
SPI1
SPI1
SPI1
SPI1
INT
Syscon
Syscon
EEPROM
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
4ma
I
I
I
I
I
I
4ma
4ma
I
I
12ma
12ma
4ma
4ma
8ma
8ma
I
8ma
8ma
8ma
8ma
I
8ma
I
I
4ma
4ma
I
I
I
I
I
I
4ma
4ma
4ma
4ma
4ma
4ma
4ma
4ma
4ma
4ma
I
I
I
4ma
PU Management data input/output
PD Receive clock in
PD Receive data in
PD Receive data valid
PD Receive data error
PU Transmit clock in
PD Transmit data out
PD Transmit enable
PD Transmit error
PD Carrier sense
PU Collision detect
Green LED
Red LED
PU EEPROM / Two-wire Interface clock
PU EEPROM / Two-wire Interface data
PD AC97 bit clock
PD AC97 frame sync
PD AC97 Primary input
PU AC97 output
AC97 reset
PD SPI bit clock
PD SPI Frame Clock
PD SPI input
SPI output
PD External interrupts
PU Power on reset
User Reset in out - open drain
Flash programming voltage control
PU Voltage sense
PU Voltage sense
PU Card detect
PU Card detect
PU Voltage detection / status change
PU Voltage detection
Data transceiver direction control
Data bus transceiver enable
Address bus transceiver enable
PU Memory card register
PU Memory card high byte select
PU Memory card low byte select
PU I/O card read
PU I/O card write
PU Memory card read
PU Memory card write
PU Ready / interrupt
PU Write protect
PU Wait Input
Card reset
Table S. Pin Descriptions (Continued)
Pin Name
EGPIO[15:0]
DD[15:8]
DD7
DD[6:0]
IDEDA[2:0]
IDECS0n
IDECS1n
DIORn
DIOWn
DMACKn
IORDY
CVDD
RVDD
CGND
RGND
Block
Pad Pull
Type Type
Description
GPIO I/O, 4 ma PU Enhanced GPIO
IDE
8ma PU IDE data bus
IDE
8ma PD IDE data bus
IDE
8ma PU IDE data bus
IDE
8ma
IDE Device address output
IDE
8ma
IDE Chip Select 0 output
IDE
8ma
IDE Chip Select 1 output
IDE
8ma
IDE Read strobe output
IDE
8ma
IDE Write strobe output
IDE
8ma
IDE DMA acknowledge output
IDE
I
PU IDE ready input
Power
P
Digital power, 1.8V
Power
P
Digital power, 3.3V
Ground
G
Digital ground
Ground
G
Digital ground
DS638PP4
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